This register might be interesting:
Code:
/*
* PCICSR: PCI control register.
* BIG_ENDIAN: 1: big endian, 0: little endian.
* RX_TRESHOLD: Rx threshold in dw to start pci access
* 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
* TX_TRESHOLD: Tx threshold in dw to start pci access
* 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
* BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
* ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
* READ_MULTIPLE: Enable memory read multiple.
* WRITE_INVALID: Enable memory write & invalid.
*/
#define PCICSR 0x008c
#define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
#define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
#define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
#define PCICSR_BURST_LENTH FIELD32(0x00000060)
#define PCICSR_ENABLE_CLK FIELD32(0x00000080)
#define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
#define PCICSR_WRITE_INVALID FIELD32(0x00000200)
By default this register is initialized as:
Code:
rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
rt2x00pci_register_write(rt2x00dev, PCICSR, reg);