Hi olovh,
Thanks for the logs.
I don't find any endianizing logic in the writel, readl expansions as supplied by kernel.org. I believe the reason is that a PCI device retains its endianness regardless of the host byte order. I think it is possible to do otherwise, but for reasons of manufacturing economy, vendors don't usually do so. If the kernel you're working with has been tweaked to do different, we may have problems. If it has, could you post a snippet of the expansions?
It looks like there may be a problem with the compiler constants. For example, looking at the compiler constants where the compile target is a PPC machine running in big endian mode, we get:
Code:
...
#define __BIG_ENDIAN__ 1
...
#define _BIG_ENDIAN 1
...
Looking at the gcc compiler constants you supplied, I don't see anything specifying big endianness. This means the driver is being compiled for a little endian target. So it may be worth while to double check this.
As an experiment, it also may be informative to go to rt_config.h and add
Code:
#define BIG_ENDIAN TRUE
after line 41 and see what happens.
Googling around for code snippets, it really looks like endian1.patch has the right idea. endian4.patch.gz reverts to the original endianization, but includes the extra debug info for NICLoadFirmware().
Thanks,
edit:
I was getting a not logged in message when I tried your link earlier. Now that I have gotten in, I see where indeed there's endian conversion in readl. Try my suggestion for BIG_ENDIAN above, but do not apply the patch. We'll see what happens.
Thanks again,